Emulator
What	We are designing a parallel fabric that is tailored to emulating digital hardware designs written in Chisel. The fabric is also designed to map well to existing FPGAs.
Which	A Chisel design of a processing element and routing fabric.
Why	Fast hardware emulation is key to accelerating the design cycle. Faster to design, debug, test, and evaluate. Generalizable to other domains.
Who	Jonathan Bachrach and Andrew Waterman and Krste Asanovic
How	Chisel
When	2012-present
Where	UC Berkeley EECS
And	chisel